The present invention relates to a semiconductor package, and more particularly to a semiconductor package comprising Lead on Chip type inner leads and standard type inner leads.
FIG. 16 is a plan view showing a conventional semiconductor package which has been disclosed in Japanese Unexamined Patent Publication No. 10-242373(1998), for example. In FIG. 16, a sealing resin of the semiconductor package is illustrated in a two-dotted chain line. FIG. 17 is a sectional view taken along a line XVIIxe2x80x94XVII in FIG. 16 and FIG. 18 is a sectional view taken along a line XVIIIxe2x80x94XVIII in FIG. 16. In FIG. 16, central electrode pads 7a are arranged on the center of a upper surface of a semiconductor chip 1 and LOC type inner leads 3a are extended to the upper surface of the semiconductor chip 1. Each central electrode pad 7a is electrically connected to a respective LOC type lead 3a through a metal wire 4. Moreover, peripheral electrode pads 7b are formed around the upper surface of the semiconductor chip 1 and standard type inner leads 6a are arranged on the outside of the outer periphery of the semiconductor chip 1. Each peripheral electrode pad 7b is electrically connected to a respective standard type inner lead 6a through the metal wire 4. The term xe2x80x9ca LOC (Lead on Chip) type inner leadxe2x80x9d means an inner lead extended to a upper surface of a chip, while xe2x80x9ca standard type inner leadxe2x80x9d means an inner lead arranged on the outside of the periphery of the chip and not extended to the upper surface.
In a conventional semiconductor package, the LOC type leads 3 are bent and displaced by S in their upper direction and fixed to the semiconductor chip 1 with an adhesive tape or adhesive 2, as shown in FIG. 17.
On the other hand, as shown in FIG. 18, the standard type inner leads 6a are provided on the outside of the outer periphery of the semiconductor chip 1 and on a plane lower, by a bent portion S, than a plane on which the LOC type inner leads 3a are formed. Each standard type inner lead 6a is electrically connected through the metal wire 4 to the respective electrode pad 7b provided on the upper surface of the semiconductor chip 1. The semiconductor chip 1, the adhesive 2, the LOC type inner leads 3a, the standard type inner leads 6a and the metal wires 4 are sealed with a sealing resin 5.
In the conventional semiconductor package constituted as described above, since the semiconductor chip 1 is supported with the LOC type leads 3 through the adhesive 2, a volume ratio of the semiconductor chip 1 to the sealing resin 5 can be enhanced. More specifically, a semiconductor chip having a great size can be sealed in a sealing resin having a small volume. On the other hand, each section shown in FIGS. 17 and 18 is constituted by only the semiconductor chip and the sealing resin. Therefore, a modulus of section of the semiconductor package as a combined beam is small, thus a stress caused by an outer load increases.
The sealing using a resin is carried out using a mold, and the semiconductor package is pushed out of the mold using eject pins. When eject pin receiving portions 8 of the sealing resin shown in FIG. 16 are pushed up by the eject pins (not shown) so as to remove the semiconductor package from the mold, stress on the semiconductor chip is increased if the section modulus is reduced. Moreover, since the size of semiconductor chips is being reduced from year to year, resulting in a greater reduction in the sectional modulus and an increasing stress is applied to the semiconductor chip.
Furthermore, the conventional semiconductor package requires a region coated with the adhesive 2 on the upper surface of the semiconductor chip 1 in order to adhere the LOC type leads 3, and the electrode pads 7 cannot be provided in the region coated with the adhesive 2. For this reason, the area on the chip 1 for arranging the electrode pads 7 is restricted to the central region (for the central electrode pads 7a) and the peripheral regions (for the peripheral electrode pads 7b) along shorter sides where the standard type leads 6 are provided. Thus, there has been a drawback in that the region on the upper surface of the semiconductor chip where the electrode pads 7 are to be provided is limited to a small I-shaped region.
Furthermore, since the LOC type leads 3 and the standard type leads 6 are processed down to a working limit, each modulus of section in thickness and width directions is small and a bending rigidity is also small. Moreover, since tips of the LOC type leads 3 and tips of the standard type leads 6 are provided on different planes, they are easily deformed when being taken out of or accommodated in a delivery magazine during a delivery or an inspection at an assembling step.
In the conventional semiconductor package shown in FIG. 16, the S bend of LOC type lead 3 must be located at a region in which the leads 3 are arranged rectilinearly, in parallel, in the vicinity of the outer leads 3b extending from the sealing resin. If the S bend of the LOC type lead 3 is located at a region in which the leads 3 are arranged obliquely, spacing between tips of the adjacent LOC type inner leads 3a easily becomes uneven so that the tips of the adjacent leads come in contact with each other or necessary space cannot be obtained. In the conventional semiconductor package shown in FIG. 16, leads 6 on four corners have no bent portion and other leads 3 are bent so that the leads 6 and the leads 3 are not in the same plane. Accordingly, there have been drawbacks in that a high working cost for bending is required and leads must be handled carefully so as not to be deformed.
The structure of the conventional semiconductor package described above is suitable for a simple function semiconductor device incorporating a standardized chip such as an ordinary DRAM or SRAM chip. However, with the above-mentioned conventional structure, a semiconductor chip of high function having a large size and electrode pads distributed and arranged on its whole upper surface, e.g. a chip in which a DRAM cell, a SRAM cell and a peripheral circuit cell are integrated, cannot be constituted as a semiconductor package.
In order to solve the above-mentioned drawbacks, it is an object of the present invention to provide a semiconductor package which incorporates a high-function semiconductor chip, such as one wherein a DRAM cell, a SRAM cell and a peripheral circuit cell are integrated, having electrode pads distributed and arranged on its whole upper surface.
It is another object of the present invention to provide an inexpensive and high-quality semiconductor package wherein LOC type inner leads and standard type inner leads are arranged on a single plane and electrically connected to electrode pads on a semiconductor chip through metal wires.
Moreover, the semiconductor chip is enlarged through an increase in a memory capacity and an addition of functions. Correspondingly, the outer dimension of a sealing resin is increased. Consequently, when the semiconductor package is to be removed from a mold, a bending moment generated in the central part of the semiconductor package is increased. It is yet another object of the present invention to provide a semiconductor package having a high rigidity which is resistant to the great bending moment, especially the sealing resin is at a high temperature immediately after a sealing step.
In order to achieve the above-mentioned objects, the present invention provides a semiconductor package in which a semiconductor chip, a die pad, a die bond material fling the semiconductor chip on the die pad, LOC type inner leads having their tips extended above the semiconductor chip and metal wires connecting the tips of the LOC type inner leads to electrode pads on the semiconductor chip are sealed with a sealing resin, wherein outer leads formed successively to the inner leads are protruded outwardly from the sealing resin.
Moreover, the present invention provides a semiconductor package in which standard type inner leads and metal wires connecting the tips of the standard type inner leads to electrode pads on the semiconductor chip are further sealed with the sealing resin, wherein outer leads formed successively to the standard type inner leads are protruded outwardly from the sealing resin, and the LOC type inner leads and the standard type inner leads are arranged on a same plane.
Furthermore, the present invention provides a semiconductor package in which a clearance between the LOC type inner leads and the die pad is set to be larger than a sum of thickness of the semiconductor chip and the die bond material.
And more, the present invention provides a semiconductor package in which the LOC type inner leads and the standard type inner leads are mixedly arranged along at least a side of the semiconductor chip.
Alternatively, the present invention provides a semiconductor package in which the LOC type inner leads are arranged along a side of the semiconductor chip and the standard type inner leads are arranged along another side of the semiconductor chip.
In a semiconductor package according to the present invention, a distance between upper surfaces of the outer leads and the upper surface of the sealing resin is different from a distance between lower surfaces of the outer leads and the lower surface of the sealing resin, and ends of the die pad are exposed in opposed side surfaces of the sealing resin and being on a plane parallel with a plane on which the leads are protruded.
Fuethermore, the present invention provides a semiconductor package in which at least a semiconductor chip, metal wires, LOC type inner leads having their tips extended above the semiconductor chip and standard type inner leads having their tips arranged outside of periphery of the semiconductor chip are sealed with a sealing resin, wherein the semiconductor chip has distributed electrode pads distributed and arranged on its upper surface and has at least either central electrode pads rectilinearly provided in a central region of the semiconductor chip or peripheral electrode pads provided along the periphery of the semiconductor chip, and the LOC type inner leads and the standard type inner leads are arranged on a same plane and mixedly arranged along a side of the semiconductor chip.
A semiconductor package of the present invention is manufactured with the steps of forming a die pad frame in which die pads are surrounded with a frame, depressing the die pad to make a displacement between the die pad and the frame, bonding a semiconductor chip to the die pad with a die bond material, superposing a lead frame, in which inner leads are surrounded with a frame, on the die pad frame so as to interpose the semiconductor chip between the die pads and the inner leads, welding the frame of the die pad and the frame of the lead frame together, sealing the die pad, the semiconductor chip and the inner leads with a sealing resin, and removing the frame of the die pad and the frame of the lead frame away.
Additional objects, advantages, and novel features of the invention shall be set forth in part in the description that follows and in part will be apparent to those skilled in the art upon examination of the following or may be learned by the practice of the invention. The objects and the advantages of the invention may be realized and attained by means of the instrumentalities and in combinations particularly pointed out in the appended claims.